1. Field of the Invention
The present invention relates to semiconductor processing and more particularly to a trench isolation process which prevents boron outdiffusion and decreases stress.
2. Background Information
As the demand for cheaper, faster, lower power consuming microprocessors increases, so must the device packing density of the integrated circuit (IC). Very Large Scale Integration (VLSI) techniques have continually evolved to meet the increasing demand. All aspects of the IC must be scaled down to fully minimize the dimensions of the circuit. In addition to minimizing transistor dimensions, one must minimize the dimensions of the field regions (or isolation regions) which serve to physically and electrically isolate one semiconductor device from an adjacent semiconductor device on a semiconductor substrate so that each device can operate independently of the other.
In general, the number of transistors which can be built on a silicon substrate is limited only by the size of the transistors and the available surface area of the silicon substrate. Transistors can only be built in active regions of a silicon substrate while isolation regions of the substrate are dedicated to separating active regions from one another. Therefore, to maximize the number of transistors on the surface of a silicon substrate, it is necessary to maximize the available active surface area of the substrate. The active surface area is maximized by, in turn, minimizing the isolation regions of the silicon substrate. In order to fully minimize an isolation region, the width of the isolation region should approach the minimum width printable by a given photolithographic technology.
One technology which has been developed to form such isolation regions is known as trench technology. A trench isolation structure is formed in a silicon substrate by etching a trench region into the substrate and subsequently refilling this trench with some type of trench fill material. Thereafter active regions adjacent to the trench isolation structure are available for conventional semiconductor processing to form transistors or the semiconductor device.
The material used to fill the trench formed in the semiconductor substrate plays an important roll in the robustness and isolation quality of the trench isolation structure. Typically the trench is filled with a dielectric material such as, for example, a silicon dioxide (oxide).
One example of a prior art method for forming trench isolation structures is illustrated in FIGS. 1a-k. FIG. 1a illustrates a semiconductor substrate 110 with a pad oxide layer 120 and a polish stop layer 130 deposited thereon. Polish stop layer may be made of a nitride, for example silicon nitride. Polish stop layer 130 and pad oxide layer 120 are then patterned and etched to form an opening 140, as is illustrated in FIG. 1b. It will be obvious to one with ordinary skill in the art that polish stop layer 130 and pad oxide layer 120 may be patterned using well known photolithographic masking and etching techniques (not shown).
After polish stop layer 130 and pad oxide 120 are patterned the substrate 110 is etched to form a trench 145, as is illustrated in FIG. 1c. After trench 145 is etched however the sidewalls of the trench are not clean, thus a preclean step is performed to remove debris from the trench sidewalls. Next, a sacrificial oxide 150 is formed in the trench, as is illustrated in FIG. 1d. Sacrificial oxide 150 is then removed leaving the sidewalls clean and free of debris, as is illustrated in FIG. 1e.
Trench sidewall oxide 160 is then formed in the trench, as is illustrated in FIG. 1f. Trench sidewall oxide 160 is a higher quality (or is purer) than sacrificial oxide 150 and remains in the trench. Next the trench is filled in with an oxide to form trench fill oxide 170, as is illustrated in FIG. 1g. It should be noted and it will be obvious to one with ordinary skill in the art that the trench may be filled with oxide using chemical vapor deposition (CVD) techniques. After the trench is filled, trench fill oxide 170 is then polished in order to remove the excess oxide above polish stop layer 130, as is illustrated in FIG. 1h.
As illustrated in FIG. 1i, polish stop layer 130 is then removed. It should be noted and it will be obvious to one with ordinary skill in the art that polish stop layer 130 may be removed using conventional etch techniques. After polish stop layer 130 is removed, an etch-back step is performed in order to isolate trench sidewall oxide 160 and trench fill oxide 170 within the trench, as is illustrated in FIG. 1j. It should be noted and it will be obvious to one with ordinary skill in the art that this etch-back step may be performed using chemical mechanical polishing (CMP) techniques.
There are several problems that result from the use of trench isolation technology. One such problem is the formation of the "birds beak" or sharp top corners 190 of the trench, as is illustrated in FIG. 1j. Sharp top corners 190 of the trench may carry stronger electromagnetic fields (e-fields). Sharp top corners of the trench cause problems when later forming active regions on either side of the trench. For example, when forming a transistor adjacent to the trench a gate insulating oxide layer is grown over the substrate and over the trench, because the top, corners of the trench are sharp, the gate oxide layer cannot be grown with a uniform thickness. As illustrated in FIG. 1k, the thickness of the thin gate oxide layer 180 around the top corners 190 becomes very thin. The thin gate oxide layer may break down if subjected to high electromagnetic field. For example, once a transistor is formed and is functioning the sharp top corners 190 create a high e-field and the thin gate oxide 180 may be subject to failure causing undesirable parasitic capacitances and leakage voltages which degrade device performance.
Sharp top corners also cause a problem when filling the trench. As stated above, the trench is generally filled using chemical vapor deposition (CVD) techniques to fill the trench with materials such as an oxide, polysilicon, or a combination thereof. CVD processes subject the structure to plasma which also induces (or creates) an electric field around the sharp corners causing a non-uniform deposition process and may create gaps or voids in the trench fill.
Another problem that results from trench isolation technology is the outdiffusion of dopants from the semiconductor device region, for example from the source 220 and drain 230 regions of a transistor (illustrated in FIG. 2), into the trench 245 region. Outdiffusion is especially prominent in N-channel transistors that have narrow widths, thus as device dimensions decrease (e.g. narrower widths) the susceptibility to outdiffusion increases. Outdiffusion of the dopants from the device region has several effects. It is well known in the art that the higher the dopant concentration the higher the threshold voltage of the transistor. Thus, outdiffusion of the dopants from the device region into the channel reduces the dopant concentration of the transistor and thereby decreases the threshold voltage of the device. For example, if the dopants in the region 250 adjacent source region 220 outdiffuse into the trench 245, then the dopant concentration in region 250 will be less than the dopant concentration in region 255. Therefore, the threshold voltage in region 250 will be less than the threshold voltage in the region 255.
The outdiffusion of dopants may also increase the off-leakage current. The off-leakage current is the parasitic (i.e. bad or unwanted) current that flows from the source 220 to the drain 230 of the transistor when the voltage applied to the gate 240 is zero (V.sub.g =0), and the drain voltage (V.sub.d) is at power supply voltage (V.sub.cc) (i.e. in general a power supply may be V.sub.cc =1.8 volts). It is desirable for the off-leakage current to be minimized such that the voltage at the source is zero (V.sub.s =0). However, if the dopants outdiffuse into the trench, for example dopants near the source region (for example, dopants from region 250) diffuse into the trench, then the threshold voltage near the source region becomes less than the threshold voltage in the channel and drain regions and may allow parasitic current to flow from the source 220 to the drain 230.
One prior art method used to decrease the outdiffusion of the dopants into the trench is to treat the sidewall oxide 160 with a nitrogen plasma in order to transform the surface of sidewall oxide 160 into a nitrogen-rich oxide surface. By creating a nitrogen-rich oxide surface the dopants do not diffuse as easily into the trench. However, it has been found that the use of just a nitrogen plasma does not create a sufficient barrier to control the outdiffusion of the dopants. The use of nitrogen plasma creates a barrier in some regions but nitrogen alone does not react enough with the oxide layer in order to form a complete barrier. Thus, outdiffusion of the dopants still occurs and parasitic currents continue to be a problem.
A further problem with the prior art isolation techniques described above is that they work for devices which use a thin gate oxide layer of greater than 32 .ANG., however as device characteristics shrink the above described trench isolation technology fails as the gate oxides become thinner (32 .ANG. or less). In other words, as device dimensions move from 0.35.mu. technology to 0.251.mu. technology and lower prior art trench isolation technology is inadequate.
Thus, what is needed is a trench isolation structure and a method for making that structure that will prevent dopant outdiffusion, will also allow uniform deposition of thin gate oxides, and will permit the use of thinner gate oxides.